ECL (emitter--coupled logic) drivers have been used as output buffers and drivers. Although such devices have served the purpose, they have not proven entirely satisfactory under all conditions of service because they produce short (on the order of 0.5 nanosecond) transition (rise and fall) times. Such short transition times, for example for a driver resident on a printed circuit board, can create reflections in the conductive line(s) leading from the output of such a driver. These lines can appear on printed circuit boards, backplanes, cabling, etc. Such reflections produce noise in those lines. Such reflections can occur anywhere on the conductive line(s) connected to the output of the driver. Such reflections can occur anywhere on such lines(s) from the output of the driver to the end(s) of the line(s). For example, a sufficiently fast transition time can cause a signal reflection at a downstream receiver, which reflection would be returned to the driver output, producing unwanted noise.
Present ECL technology provides output driver transition times (rise and fall times) in the sub-nanosecond range. In certain applications and designs, it is advantageous to purposely slow down these transition times in order to minimize noise.
One response to this problem has been to slow down the driver transition times in the manner shown in prior art FIG. 1. FIG. 1 shows an ECL cutoff driver 10 wherein the input signal IN to the driver is provided to the emitter follower 12 formed by transistor TI and resistor RI. Driver 10 further includes a current switch 14, current source 16 and output emitter follower (OEF) or output buffer 18. Current switch 14 includes a NOR switch or NOR side 20 and an OR switch or OR side 22. The transistors of current source 16 are biased up by reference voltage V.sub.ref 2 so that current source 16 serves as a constant current generator, so voltage V.sub.EE pulls constant current through either side 20 or 22 of current switch 14. Input signal IN and reference voltage V.sub.ref 1 determine which side 20 or 22 of current switch 14 is to be turned "on"; both sides of switch 14 are "on" only during transitions. Current switch 14 is provided with a load or "swing" resistor 24. Capacitor 26 is placed between the base and collector of OEF 18, and thus across current switch 14 load resistor 24. Capacitor 26 is placed across load resistor 24 to slow down the driver 10 transition times. This technique is operable, but has a disadvantage in that the resulting output rise time TR is approximately 1.5 times the resulting fall time TF, thus causing the propagation delay TD++ (propagation delay when driver 10 input and output are both going positive) to increase more than the increase in fall time, thus resulting in slower circuit performance. This substantial increase in TD++ when attempting to adjust the fall time TF of the driver is therefore undesirable.
ECL drivers can be categorized as cutoff drivers and non-cutoff ("normal") drivers. Operation of cutoff and non-cutoff drivers is distinguished by low-state output voltage level V.sub.OL and by operation of the OEF in the driver's low state. For a cutoff driver, V.sub.OL =V.sub.TT (terminating voltage) which can be accomplished by turning off (cutoff of) the OEF transistor(s). For a non-cutoff driver, V.sub.OL is higher, and the OEF is not cutoff. Cutoff drivers and non-cutoff drivers can have the same schematic diagrams or component interconnections, but have some different component and operating (voltage or current) values.
As shown in FIG. 1, a present method used to slow down the fall time of an ECL cutoff driver is to place a capacitor 26 across the swing or load resistor 24 in current switch 14. This then provides a time constant of R (resistance of load resistor 24) times C (capacitance of capacitor 26) which causes the base voltage of output emitter follower 18 to rise and fall exponentially. The effect of this at the emitter of OEF 18 is that the resulting rise time is approximately 1.5 times greater than the resulting fall time, causing the TD++ propagation delay to increase essentially the same amount as the increase in rise time. This disproportionate increase in rise time versus fall time results because during the rise time, the base of OEF 18 must rise to a voltage sufficient to turn the OEF on, and during rise time the rate of change of the base voltage, being exponential, has diminished. The opposite is true during the fall time; during the fall time, the emitter of OEF 18 responds during the greatest rate of change of the OEF base voltage. These transition times are illustrated in prior art FIG. 2.
In the device of FIG. 1, resistor 24 can for example be 290 ohms, resistor RE can for example be 97 ohms, resistor RI can for example be 13 K ohms, resistor RO can for example be 25 ohms, current source 16 can for example be configured to produce 4.5 milliamperes, capacitor 26 can for example be 6 picofarads, reference voltage V.sub.ref 1 can for example be -2.157 reference volts, voltage V.sub.ref 2 can for example be -3.879 volts, voltage V.sub.ee can for example be -5.2 volts, and load termination voltage or terminating voltage V.sub.TT can for example be -2.0 volts.
Results of a simulation of the driver of FIG. 1, using SPICE (Simulation Program with Integrated Circuit Emphasis) integrated circuit simulation software, is given in FIG. 2, and in Table 0 below. For that simulation, "swing" resistor 24 was set to 290 ohms, current source 16 produced a constant current of 4.5 milliamperes, driver output rise time TR and driver output fall time TF were measured from 20% to 80%, propagation delay TD++ (defined above) and propagation delay TD-- (propagation delay when driver 10 input and output are both going negative) were measured from 50% of the driver input to -1.3 V on the output, time is shown in the last four columns in nanoseconds, and the first column shows different values of capacitor 26. Voltages, RE, RI and RO were set as described in the preceding paragraph. A suitable pulse input, and a suitable simulated load at the output, were used for the simulation. SPICE is discussed in Antognetti, P. and Massobrio, G., eds. Semiconductor Device Modeling with SPICE (McGraw-Hill, New York, 1988).
TABLE 0 ______________________________________ C(pF) TR(ns) TF(ns) TD++(ns) TD--(ns) ______________________________________ 0 0.74 0.61 1.07 0.73 1.0 0.94 0.71 1.36 0.80 2.0 1.21 0.88 1.67 0.92 3.0 1.52 1.07 1.99 1.02 4.0 1.84 1.27 2.31 1.12 5.0 2.19 1.50 2.64 1.21 6.0 2.54 1.73 2.98 1.30 ______________________________________
The above data is for an ECL cutoff driver. For an ECL non-cutoff driver, resistor 24 could for example be 330 ohms, and current source 16 could for example be configured to produce 3.0 milliamperes.
Thus, a prior art approach to slowing down output rise time and output fall time for ECL drivers causes a disproportionately larger increase in output rise time compared with output fall time, so that any resulting noise reduction is obtained with an undesirable increase in delay. In this prior art approach, output rise time is slowed more than is output fall time. Thus, to sufficiently increase output fall time for effective noise reduction, an additional increase in output rise time is required, beyond what would be necessary for effective noise reduction for rising transitions. It is therefore also desirable to at least substantially independently control rise time and fall time, in order to reduce noise while limiting the delay resulting from that noise reduction.